1. Field of the Invention
The present invention relates to a thin-film transistor and a liquid crystal display device, and more particularly, to a thin-film transistor, a fabrication method thereof, a liquid crystal display device using the same, and a fabrication method thereof.
2. Description of the Related Art
In recent years, with rising interests in information displays and increasing demands to use portable information media, researches and commercialization of light-weight and thin-profile flat panel displays (FPDs) for substituting traditional displays such as cathode ray tubes (CRTs) have been actively carried out. In particular, among those flat panel displays, a liquid crystal display (LCD) as a device for expressing an image using optical anisotropy of liquid crystals has been actively used in notebooks, desktop monitors, and the like due to its excellent resolution, color expression, image quality, and the like.
An active matrix (AM) method, which is a driving method primarily used in the liquid crystal display, is a method of driving the liquid crystals of a pixel unit using an amorphous silicon thin-film transistor (a-Si TFT) as a switching element.
The liquid crystal display may largely include a liquid crystal panel for displaying an image, a backlight unit for emitting light to the liquid crystal panel, and a driving circuit unit for applying and controlling a signal voltage to the liquid crystal panel and backlight unit
Hereinafter, the schematic structure of a typical liquid crystal display will be described below in detail with reference to FIG. 1. FIG. 1 is a cross-sectional view schematically illustrating a liquid crystal display in the related art. As illustrated in FIG. 1, the liquid crystal display may include a color filter substrate 87, a thin-film transistor array substrate 10, and a liquid crystal layer 97 interposed between the color filter substrate 87 and the thin-film transistor array substrate 10.
The color filter substrate 87 and thin-film transistor array substrate 10 are bonded by a sealant (not shown) formed at the outside of an image display region to face each other, and the bonding between the color filter substrate 87 and thin-film transistor array substrate 10 is implemented through an alignment key (not shown) formed on the color filter substrate 87 or thin-film transistor array substrate 10.
A thin-film transistor (not shown) is formed on the thin-film transistor array substrate 10, and the thin-film transistor may include a gate electrode 20 constituting part of the gate line (not shown), a source electrode 44 connected to the data line (not shown), and a drain electrode 45 connected to the pixel electrode 80.
Furthermore, the thin-film transistor may include an active layer 40 forming a conductive channel between the source electrode 44 and drain electrode 45 by a gate voltage supplied to the gate electrode 20.
An ohmic contact layer 41 is formed between the active layer 40 and the source electrode 44 and the drain electrode 45 to provide an electrical contact between the active layer 40 and the source and drain electrodes 44, 45 in an efficient manner.
Part of the source electrode 44 is extended in one direction to constitute part of the data line, and part of the drain electrode 45 is extended toward the pixel area and electrically connected to the pixel electrode 80 through a contact hole formed at the insulating layer 60.
Furthermore, as described above, a color filter 95 having a plurality of sub-color filters for implementing red, green and blue colors, a black matrix 90 for dividing between the sub-color filters and blocking light passing through the liquid crystal layer 97, and a common electrode 85 for applying a voltage to the liquid crystal layer 97 are formed on the color filter substrate 87.
On the other hand, a silicon oxide layer (SiO2) or silicon nitride layer (SiNx) may be used for an insulating layer 30 between each constituent element constituting the thin-film transistor, and a chemical vapor deposition (hereinafter, referred to as “CVD”) process may be used for the formation method. The chemical vapor deposition (CVD) process is a process of isotropic deposition in the direction from top to bottom. Accordingly, when a wiring is formed in a protruded manner with a predetermined thickness on the upper surface of the substrate, a thickness difference due to the wiring may not be compensated even if the insulating layer 30 is formed using the CVD process.
Meanwhile, a thickness of the gate electrode varies as the resolution of a liquid crystal display is developed from full high definition (FHD) to ultra dimension (UD). In other words, the transmission of a lot of information is required to implement such high resolution, and an area of the gate electrode applying a gate voltage to one pixel of the liquid crystal display should be enlarged to solve the problem. However, the enlarged area of the gate electrode causes a reduced aperture ratio of the liquid crystal display, and thus studies have been carried out in the direction of increasing a thickness of the gate electrode rather than enlarging an area of the gate electrode.
FIG. 2 is an enlarged cross-sectional view of a portion “A” of FIG. 1, illustrating the cross-sectional structure of a gate insulating layer formed by CVD on an upper portion of the gate electrode constituting a thin-film transistor. Referring to FIG. 2, it is seen that a thickness (t1) of the gate insulating layer 30 formed at an upper portion of the gate electrode 20 is identical to a thickness (t1) of the gate insulating layer 30 at an upper portion of the substrate 10.
However, a thickness (t2) of the gate insulating layer 30a covering a lateral surface 20a of the gate electrode 20 formed at a predetermined taper angle is less than a thickness (t1) of the gate insulating layer 30 at an upper portion of the gate electrode 20 and substrate 10. The thickness (t2) of the gate insulating layer 30a covering a lateral surface 20a of the gate electrode 20 formed at a predetermined taper angle is less than the thickness (t1) of the gate insulating layer 30 at an upper portion of the gate electrode 20 and substrate 10 because the thickness of a layer formed at an inclined surface having a predetermined angle is less than that of a layer formed at the plane surface due to its isotropic deposition.
On the other hand, as illustrated in FIG. 2, when an active layer 40 having a thickness of about 1000 Å is deposited on the gate insulating layer 30 as a subsequent process, a disconnected portion of the active layer 40 may occur on an inclined portion, namely, gate insulating layer 30a as illustrated in a portion “F” of FIG. 2 due to a step height of more than about 8000 Å. In other words, since a deposition thickness of the active layer 40 is very low, about 1000 Å, and thus it causes a phenomenon in which the active layer 40 is not formed on a surface of the gate insulating layer 30a corresponding to an inclined portion of the gate insulating layer 30 when forming it on the gate insulating layer 30a having a large step height.
In this case, a hole is formed on a lateral surface of the gate electrode 20 during the etching process carried out as a subsequent process, thereby exposing part of the gate electrode 20. The exposed gate electrode 20 may create a short phenomenon due to a relation between the source and drain electrodes formed at an upper portion of the gate electrode 20. In particular, as illustrated in the portion “F” of FIG. 2, when a protrusion or inverse taper angle is formed at an edge portion of the gate insulating layer 30 on an upper surface of the gate electrode 20, a disconnection portion of the active layer 40 may occur at a lateral surface of the gate electrode 20 during the subsequent process.
FIG. 3 is an enlarged cross-sectional view of a portion “A” of FIG. 1, illustrating the cross-sectional structure of a gate insulating layer formed by CVD at an upper portion of the gate electrode constituting a thin-film transistor. Referring to FIG. 3, a thickness (t3) of the gate insulating layer 30 is formed in a thick manner, for example, at a thickness of more than about 6000 Å, to prevent the deposition thickness (t2) at a lateral surface portion 30a of the gate insulating layer 30 from being formed at a low thickness as illustrated in FIG. 2. The lateral surface portion of the gate insulating layer 30, namely, a thickness (t4) of the gate insulating layer 30a, is formed higher than the thickness (t2) of the gate insulating layer 30a in FIG. 2 to enhance the coverage stability of the inclined portion, thereby suppressing the active layer 40 formed during the subsequent process at a lateral surface of the gate electrode 20 from being disconnected.
However, when a thickness of the gate insulating layer 30 is formed higher than that of the existing gate insulating layer in FIG. 2, for example, the thickness (t3) of the gate insulating layer 30 becomes too high to prevent an electric field from being sufficiently applied to the active layer 40, thereby deteriorating the electrical characteristics of elements such as on-current, VHR, or the like.